An integrated silicon double bridge anemometer

Integrated Capacitance Bridge An integrated capacitance bridge for high-resolution, wide temperature range quantum capacitance measurements

An integrated capacitance bridge for high-resolution, wide temperature range quantum capacitance measurements Arash Hazeghi, 2 Joseph A. Sulpizio, 3 Georgi Diankov, David Goldhaber-Gordon, a) and H.S. Philip Wong These authors contributed equally to this work Department of Electrical Engineering, Stanford University Department of Physics, Stanford University Department of Chemistry, Stanford Un...

Planarised optical fiber composite using flame hydrolysis deposition demonstrating an integrated FBG anemometer.

This paper reports for the first time a planarised optical fiber composite formed using Flame Hydrolysis Deposition (FHD). As a way of format demonstration a Micro-Opto-Electro-Mechanical (MOEMS) hot wire anemometer is formed using micro-fabrication processing. The planarised device is rigidly secured to a silicon wafer using optical quality doped silica that has been deposited using flame hydr...

Germanium-on-Silicon for Integrated Silicon Photonics

To meet the unprecedented demands for data transmission speed and bandwidth silicon integrated photonics that can generate, modulate, process and detect light signals is being developed. Integrated silicon photonics that can be built using existing CMOS fabrication facilities offers the tantalizing prospect of a scalable and cost-efficient solution to replace electrical interconnects. Silicon, ...

Integrated Silicon Optoelectronics - Preamble

Dark silicon management: an integrated and coordinated cross-layer approach

This paper presents an integrated and coordinated cross-layer sensing and optimization flow for distributed dark silicon management for tiled heterogeneous manycores under a critical temperature constraint. We target some of the key challenges in dark silicon for manycores, such as: directly focusing on power density/temperature instead of considering simple perchip power constraints, consideri...